IP core是预先设计好、经过严格测试和优化过的电路功能模块，如乘法器、FIR滤波器、PCI接口、以太网接口等，并且一般采用参数可配置的结构，方便用户根据实际情况来调用这些模块。随着FPGA规模的增加，使用IP core完成设计已成为发展趋势。
北京麦克沃根科技有限公司可为用户提供大量成熟高效的IP core，涵盖了IO接口、处理器、通信和网络、信号处理等不同领域，可满足不同用户的需求。
IP core模块主要包括：
● IO接口
STAT 3.0 Host/Slave
USB 3.0 Host/Device
HDMI 2.0 Master/Slave
PCI 32-bit Master/Target
PCI 64-bit Master/Target
RapidIO Physical Layer
Utopia Level 2 Slave
Utopia Level 2 MasterHyperTransport
RapidIO II
SDI Interface (SD, HD)
DVI Master/Slave等
● 通信
High Speed Viterbi Decoder
Low Speed Viterbi Decoder
Reed-Solomon Encoder/ Decoder
Shared Reed-Solomon Library
Triple-Speed Ethernet
10G Ethernet MegaCore
2.5Gb/40Gb/100Gb Ethernet MAC
Ethernet MAC
Low Latency 10/40/100Gbps Ethernet MAC/PHY
2.5Gb Ethernet PHY
10/40/100G EFEC
10/100G GFEC
Interlaken 40G 8L/100G 12L/150G 24L
Interlaken 50/100/200/400G等
● 内存控制器
Legacy DDR/DDR2 SDRAM Memory Controller
Legacy DDR/DDR2 Shared Library
DDR/DDR2/3 High Performance Memory Controller
QDR II SRAM Controller
RLDRAM II Memory Controller
ALTMEMPHY等
● 处理器
Nios II Embedded Processor Encrypted output
Nios II Embedded Processor Clear Text output
MP32 MIPS-based Processor for FPGA等
● 信号处理&图像处理
Floating Point Arithmetic Library
FIR
NCO
FFT/IFFT
Triple Buffer
Clocked Video to Image Stream Convertor
Image Stream to Clocked Video Convertor
Chroma Resampler
Color Pattern Converter IP
Color Space Converters
Median Filter
Alpha Blending Mixer
Deinterlacer等
● 其他
POS PHY L2-Link/PHY
POS PHY L3-Link/PHY
POS PHY L4 (SPI 4.2)
Shared POS PHY Library等